Today's miniaturization requirements for organic circuitized substrates, including multilayered printed circuit boards (PCBs), laminate chip carriers, and the like, require the formation of multiple circuits in a minimum volume or space. These circuits typically comprise a stack of electrically conductive copper or copper alloy layers of signal, ground and/or power planes (lines) separated from each other by a layer of organic dielectric material, typically fiber-glass reinforce resin material known in the art commonly as “FR4.” Selected lines or pads of one conductive layer are often in electrical contact with selected lines and/or pads of other conductive layers using plated holes passing through the dielectric layers. The plated holes are often referred to as “buried vias” if internally located, “blind vias” if extending a predetermined depth within the board from an external surface, or “plated-thru-holes” (PTHs) if extending substantially through the board's full thickness. By the term “thru-hole” as used herein is meant to include all three types of such substrate openings.
Before placing a given circuitized substrate through the component assembly operation, it is desirable to test the substrate, including the electrical interconnection integrity thereof, to determine whether it is able to withstand the thermal/mechanical stresses experienced during the actual manufacturing assembly process and the product's end use environment. There are presently a number of accelerated stress test methods by which substrates are tested, with each test generally designed to simulate, usually in an accelerated manner, a particular stress that would cause deterioration resulting during the assembly and natural end use conditions of the substrate. In general, these accelerated stress tests involve some element of heat, humidity, or cycling between temperature extremes, and accordingly, will artificially reproduce and hasten inherent failure modes within the tested substrate. One common type of such stress tests is the accelerated thermal cycle, also referred to as “ATC”, in which the substrate is exposed to multiple cycles of hot and cold extremes. ATC tests have the effect of mechanically straining the layers of the substrate and the thru-hole interconnections (also referred to simply as interconnects) by means of repeated cycles of thermal expansion and contraction, such as occurs during assembly cycles, product on-off cycles, and outdoor environmental temperature changes. Accordingly, in ATC tests, latent defects in the board will be revealed as the cyclic stressing mechanically exercises any weak or defective element to failure. When such ATC fatigue cycling is performed on an accelerated basis, relative to what is normally experienced in manufacturing assembly and in the field, reliability predictions relating to the substrate can be derived from the test.
Various methods of performing accelerated thermal cycle tests involve the use of a specific test “coupon”, which is typically a smaller substrate (e.g., a small PCB) which can be manufactured in replicate on its own test vehicle panel, or can be manufactured concurrently on a larger product PCB, but solely for test purposes. Test coupons that are manufactured as an integral part of the actual product substrate are therefore subject to the same manufacturing conditions and processes as the larger substrate (e.g., PCB) with which the coupons are associated. Therefore, the quality of a given test coupon can be a reliable indication of the quality of its associated, larger substrate.
One ATC thermal test procedure using test coupons involves thermally cycling the test coupon by repeated exposure to hot and cold air to both heat and cool the coupon. This particular approach has been endorsed as the benchmark standard by the Institute for Interconnecting and Packaging Electronic Circuits (“IPC”). The industry standard method has been published in Mil-Standard 202F, Method 107G (also referred to in the industry simply as “Mil-T”). Although Mil-T cycling is presently sanctioned by IPC, there are a number of known drawbacks to this approach, particularly for PCB's. For example, a complete test of a given coupon may take as long as forty days for the coupon to be processed through the one hundred to one thousand cycles necessary to simulate expected life usage. Further, the operation of a Mil-T chamber can be expensive insofar as the chilled portion of the chamber typically relies upon liquid nitrogen, which is costly to ship, store, and use, and which presents certain environmental concerns. Chamber testing is further limited by the maximum high temperature, which is typically 175C, thus not allowing direct evaluation of assembly temperature cycles from assembly, which are typically at least 220C.
Variations on air-to-air chamber testing have also been developed specifically for small test coupons to increase the rate of temperature cycling, and thus decrease the total test time. One such test unit is referred to as “HATS”, or “Highly Accelerated Test System”, one known company providing such a system under this name being Integrated Reliability Test Systems, Inc., of Anaheim, Calif. The HATS system is capable of cycling coupons between −60 to 160 degrees C. and achieves faster cycling than conventional chambers due to more efficient exchange between hot and cold air, though the relatively low efficiency of heat transfer in air still limits the actual rate of coupon cycling. One publication listed 10.6 minute cycles (about 6 cycles per hour) as the cycle rate for a −40 to 145 degrees C. test. As with other chamber cycle tests, a maximum high temperature of 160 degrees C. limits the range of cycling possible, especially to represent assembly reflow temperatures. The inability to stress coupons with a reflow cycle with HATS, or other air to air chamber tests, has at least two consequences. First, direct comparisons of cycle to fail data between cold cycling and reflow cycling on the same coupon design is not possible. Second, in the common situation where some number of reflow cycles is required as preconditioning prior to a cold cycle stress test, those reflow cycles must be performed in a separate reflow oven.
Other substrate testing approaches have also been developed. Wet thermal shock is one, in which substrates are cyclically immersed in cold and hot liquids. This approach is fast due to the increased efficiency of heat transfer in the liquid. However, drawbacks of the wet thermal shock are that the cycle is uncontrolled during the hot and cold immersions, so that rate of change is a function of sample mass. Accordingly, results are sometimes not repeatable. Further, wet thermal shock does not facilitate continuous electrical monitoring during the cycling, and, as with chamber cycling, is also limited to a high temperature of less than 175 degrees C. Another method heats and cools the test coupon by exposing it to a fluidized sand bath. This method is awkward to use and maintain, and is typically limited to a low temperature of 50 degrees C. Yet another method is referred to as the “Power Cycling Technique” (“PCT”), or, more recently, as “Current Induced Thermal Cycling”. Through this method, direct current (DC) is passed through the coupon, which causes the coupon to heat up, so that the substrate is thermally stressed. A variation of this testing procedure is referred to as an “Interconnect Stress Test” (IST), one known company referring to such testing by this name being Digital Equipment Corporation of Maynard, Mass. Current Induced Thermal Cycle methods can achieve cycle rates as fast as 10 to 30 cycles per hour because the heat is generated internally within the coupon and therefore is not dependent on heat transfer through an external medium such as air or liquid, at least for the heat up part of the cycle. Temperatures up to and above assembly reflow conditions are also easily attained.
As defined herein, the present invention involves the use of a test coupon which is subjected to thermal testing through the application of DC current to the coupon to raise and lower its temperature to the extent that the thru-holes and the interconnects thereof (e.g., between the thru-hole and the adjacent conductor lines, islands or planes) are sufficiently thermally stressed to thereby enable the tester to determine if said thru-holes and associated connecting structures (e.g., adjacent “lands”) will successfully withstand the same conditions which corresponding larger substrates will be subjected to. It has been found that a main cause of thru-hole failure may be traced to significant differences in thermal expansion between the copper or other metal plating which lines the thru-hole and the surrounding substrate dielectric material (e.g., the aforementioned “FR4” material), which have significantly different coefficients of thermal expansion. When the differential expansion causes strain that exceeds the strength of the copper thru-hole plated material, a rupture intermediate the ends of the thru-hole structure may develop due to the thermal stresses generated. This undesirable occurrence may result in one or more open circuits or intermittent contacts which in turn may lead to failure of the substrate and any system in which it is utilized.
A particular problem associated with such DC voltage thermal testing is the inability to satisfactorily test each coupon across as wide temperature range to which the associated larger substrate will be eventually exposed. Present current induced thermal testing typically uses ambient temperature as the coolest temperature surrounding the test coupon, allowing the current applied through the test coupon to raise the coupon to a predetermined elevated higher temperature. Because many substrates may be required to operate at significantly lower temperatures as well as at much higher temperatures for the lowest operating temperature, testing coupons at ranges where ambient temperature is the only “low” temperature is limited. The present invention overcomes this limitation and is considered a significant advancement in the art. The following patents, all of which are incorporated herein by reference, represent various structures and methods used in testing coupons and the like.
In U.S. Pat. No. 6,521,841 (Kawaguchi), there is described a test coupon used to evaluate characteristics of multi-layer printed circuit boards. The coupon includes a multi-layer substrate which has at least first and second wiring layers. The first and second wiring layers are configured to correspond to a tested wiring layer and another wiring layer of the multi-layer printed circuit boards, respectively. Each of first and second thru-hole groups has a plurality of thru-holes which pass through the multi-layer substrate and which are arranged in an arranging direction. First and second conductor patterns provided on the first and second wiring layers, respectively, extend substantially along the arranging direction
In U.S. Pat. No. 5,701,667 (Birch et al), there is described an Interconnect Stress Testing (IST) system and a printed wiring board test coupon which is used with the IST system. The system includes a computer device and a cabinet which is used for mounting the test coupon as well as housing a number of the other components that make up the system. During a pre-cycling phase, the system determines the correct current that should be passed through the coupon in order to heat it to a predetermined temperature. After that test current value is determined, the system stress tests the coupon by passing the determined test current through the coupon. It does so for a selected number of cycles, and monitors resistance changes in the coupon during testing while recording test data. This patent also describes the test coupon, which is designed to allegedly uniformly dissipate the heat created during the stress cycling. The above system is also described in U.S. Pat. No. 5,392,219 (Birch et al), a divisional of U.S. Pat. No. 5,701,667.
In U.S. Pat. No. 5,325,068 (Rauf), the electrical resistance of specimens formed on test coupons is measured when a test voltage applied to each specimen yields a leakage current. An operational amplifier having very high impedance inputs receives the leakage current signal and generates an output voltage that is low in magnitude and varies in the leakage current. The test voltage is applied to a plurality of specimens and leakage current from each specimen is simultaneously converted by operational amplifiers whose low impedance outputs are applied through switches in a sequential fashion to an analog to digital converter whose output is fed to a central processing unit wherein the leakage current is computed in terms of the resistance of the electrical insulation under examination.
In U.S. Pat. No. 5,198,756 (Jenkins et al), there is described a wiring test system in which test probes are oriented to engage contact points on a production circuit board. The system includes a wiring integrity verification plate comprising, in combination, a thin insulative base plate, multiple contact pads and leads attached to the plate. Each of the leads extends between and interconnects two of the contact pads, whereby multiple circuit sections are formed on the board. Each circuit section includes two pads interconnected by a lead, these two pads located so as to be contacted by the probes of the wiring test system to provide an electrical continuity test.
In U.S. Pat. No. 5,172,063 (Munikoto et al), the reliability of conductive circuitry of a printed circuit board and particularly the integrity of the conductive barrels of the board's through-holes is tested by cyclically passing a current through a plurality of interconnected barrels. The current is sufficient to resistively heat the conductive barrels to a temperature at which the glass epoxy substrate adjacent each barrel reaches a transition temperature at which the glass epoxy changes state from a solid to a semi-solid. After sufficiently heating the glass epoxy, it is allowed to cool to ambient temperature. This cycle is repeated for a predetermined number of cycles and the resistance of the barrels is measured after each cycle. A measured resistance that exceeds a predetermined value indicates that one or more defects are present in the interconnected barrels.
U.S. Pat. No. 4,510,446 (Braun et al), there is described a test coupons having predetermined respective test patterns, formed in a multilayer printed circuit board simultaneously with the fabrication of the latter. The test coupons are probed with conventional electrical instruments to provide information as to the occurrence of a misregistration of any given subsurface printed plane or trace, whether or not the misregistration exceeds a specified limit, and if desired, a measure of the degree of misregistration. The foregoing is allegedly accomplished in a timely manner without the need for cross-sectioning portions of the board and the visual observation of the subsurface printed layers.
The present invention allows the substrate test operator, in which current is induced into the substrate, to select a “low” ambient temperature lower than that surrounding the apparatus housing and then test the various substrates using this temperature as the base. As mentioned, heretofore, such testing was usually conducted with an initial room temperature ambient temperature, thereby limiting the test to only said temperature as the “low” ambient. Because substrates such as PCBs very often operate at much lower ambient temperatures (e.g., during automotive and military applications), a room temperature ambient as the initial temperature is deemed unsatisfactory to fully evaluate a substrate's end use conditions. A test system capable of both very hot and very cold cycling on the same coupon provides at least two significant advantages. First, in a single test setup, the very same coupon can be exposed to a number of high temperature reflow cycles as a precondition, and then tested to failure at a different cycle to very cold temperatures. Secondly, sets of coupons such as different cells in a designed experiment can be tested to failure at very different test conditions for direct comparison on the same coupon design and test system. That is, one cell of a particular coupon can be tested to failure at a cycle from ambient to reflow conditions, while a second cell of the same coupon can be tested to failure at a cold cycle representative of extreme use conditions, both using the same test system. Techniques of acceleration modeling can then be used to quantify the relative fatigue damage and other affects of a reflow cycle vs. a field cycle. It is therefore believed that an apparatus and associated method for providing low temperatures other than ambient for this type of testing, in combination with the intrinsic fast cycle rates and the ability to also test to very high reflow temperatures on the very same coupon, will represent significant advancements in the art.